Low bit-error-rate (BER) communication of data over a communications channel is often considered an important requirement in many systems. In the case of memory devices and systems, fulfilling this requirement is increasingly difficult due to signaling and circuit limitations. In future memory devices and systems, scaling of interface circuitry to accommodate higher data rates may be restricted by transistor sensitivity and threshold limits. In addition, even though interconnect lengths and a loss tangent may be constant, the higher data rates will increase noise due to an increased bandwidth. Given constraints on interface overhead and latency, developing faster interfaces with a low BER may become more challenging and expensive. This poses a problem, since conventional interfaces in memory devices and systems typically have an extremely low BER. For example, the BER in the interface in a dynamic random access memory (DRAM) is typically less than a soft error rate in the DRAM core, i.e., less than 10−30. If the BER in the interface increases in future high-speed designs, ensuring reliability with different processes, systems and environments for conventional memory devices and systems may be difficult.
Like reference numerals refer to corresponding parts throughout the drawings.